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MK50H25PLCC Arkusz danych(PDF) 2 Page - STMicroelectronics

Numer części MK50H25PLCC
Szczegółowy opis  HIGH SPEED LINK LEVEL CONTROLLER
PDF  64 Pages
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Producent  STMICROELECTRONICS [STMicroelectronics]
Strona internetowa  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

MK50H25PLCC Arkusz danych(HTML) 2 Page - STMicroelectronics

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For added flexibility a transparent mode provides
an HDLC transport mechanism without link layer
support. This flexible transparent mode may be
easily entered and exited without affecting the
X.25 link status or the link state variables kept by
the MK50H25. In this mode no protocol process-
ing is done and it is up to the user to take care of
the upper level software. Single or extended Ad-
dress field filtering and Control field handling are
optionally supported within the transparent mode.
One of the outstanding features of the MK50H25
is its buffer management which includes on-chip
dual channel DMA. This feature allows users to
receive and transmit multiple data frames at a
time. (A conventional serial communications con-
trol chip plus a separate DMA chip would handle
data for only a single block at a time.)
The
MK50H25 will move multiple blocks of receive
and transmit data directly into and out of memory
through the Host’s bus. A possible system con-
figuration for the MK50H25 is shown in figure 1.
The MK50H25 may be used with any of several
popular 16 and 8 bit microprocessors, such as
68020, 68000, 6800, Z8000, Z80, 8086, 8088,
80186, 80286, 80386SX, etc.
The MK50H25 may be operated in either full or
half duplex mode. In half duplex mode, the RTS
and CTS modem control pins are provided. In full
duplex mode, these pins become user program-
mable I/O pins. All signal pins on the MK50H25
are TTL compatible. This has the advantage of
making the MK50H25 independent of the physical
interface. As shown in figure 1, line drivers and
receivers are used for electrical connection to the
physical layer.
DESCRIPTION (Continued)
VSS-GND
DAL07
DAL06
DAL05
DAL04
DAL03
DAL02
DAL01
DAL00
READ
INTR
DALI
DALO
DAS
BMO, BYTE , BUSRE L
BMI, BUSAKO
HOLD, BUSRQ
ALE, AS
CS
ADR
READY
RESE T
VSS-GND
24
HLDA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
48
47
46
45
44
43
42
41
40
39
38
37
36
23
22
21
20
19
18
17
16
15
35
34
33
32
31
30
29
28
27
26
25
TCLK
A18
A19
A20
A21
A22
A23
RD
DSR, CTS
TD
SYSC LK
RCLK
DTR, RTS
VCC (+5V)
DAL08
DAL09
DAL10
DAL11
DAL12
DAL13
DAL14
DAL15
A16
A17
M
K
5
0
H
2
5
DIP48 PIN CONNECTION (Top view)
MK50H25
2/64



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