PSD913F2 datasheet(26/94 Pages) STMICROELECTRONICS

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PSD9XX Family

Preliminary Information

Figure 3. Data Polling Flow Chart

START

READ DQ5 & DQ7

at Valid Address

FAIL

Program/Erase

Operation Not

Complete, Issue

Reset Instruction

PASS

Program/Erase

Operation is

Complete

YES

DQ7

DATA7

DQ5

DQ7

DATA

READ DQ7

The

PSD9XX

Functional

Blocks

(cont.)

9.1.1.6.2 Data Toggle

Checking the Data Toggle bit on DQ6 is a method of determining whether a Program or

Erase instruction is in progress or has completed. Figure 4 shows the Data Toggle

algorithm.

When the MCU issues a programming instruction, the embedded algorithm within the

PSD9XX begins. The MCU then reads the location of the byte to be programmed in

Flash to check status. Data bit DQ6 of this location will toggle each time the MCU reads

this location until the embedded algorithm is complete. The MCU continues to read this

location, checking DQ6 and monitoring the Error bit on DQ5. When DQ6 stops toggling

(two consecutive reads yield the same value), and the Error bit on DQ5 remains ‘0’, then

the embedded algorithm is complete. If the Error bit on DQ5 is ‘1’, the MCU should test

DQ6 again, since DQ6 may have changed simultaneously with DQ5 (see Figure 4).

The Error bit at DQ5 will be set if either an internal timeout occurred while the embedded

algorithm attempted to program the byte, or if the MCU attempted to program a ‘1’ to a bit

that was not erased (not erased is logic ‘0’).

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