LP1071 Advance Information, Rev. 0.5

16

Freescale Semiconductor

PRELIMINARY

Pinout and Footprint

Figure 3. LP1071 Clocks

5.1

System Clock

The LP1071 is clocked using an external crystal oscillator (XO) or a temperature compensated crystal

oscillator (TCXO) running at 40MHz with a frequency resolution of ± 20 ppm or better.

5.2

PLL Block

PLL Bypass

5.3

Low Frequency Clock

The LP1071 uses a low power 32 kHz crystal oscillator to maintain the timing during sleep.

6

Pinout and Footprint

6.1

Pinout

See Table 9 for the pin description.

Table 9. Pin Description

Pad Name

Pad Type

Direction

Description

Pin

Power and Ground Pads

VDD_IO

pvdd2dgz

N/A

3.3 V I/O power pad (22 mA per pad max current)

K1

TCXO

Clock

Control

Cuircuits

40 MHz

44 MHz

20 MHz

22 MHz

PLL

40 MHz

PLL_BYPAS

S

TCXO_BYPASS

TCXO_BYPASS_CLK

PLL_BYPASS_CLK

XTAL

32 kHz

XTAL_BYPASS

XTAL_BYPASS_CLK

88 MHz

32 kHz

ARM

AFE

Chip

Boundary

FAST_CLK_PWR