Data Sheet

ADRF5715

THEORY OF OPERATION

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Rev. 0 | 12 of 14

The ADRF5715 incorporates a 1-bit fixed attenuator array that

offers an attenuation range of 16 dB.

The ADRF5715 has a digital control input, D0, to select the desired

attenuation state in parallel mode, as shown in Figure 19. See

Table 7 for the truth table.

Table 7. Truth Table

Digital Control Input (D0)

Attenuation State (dB)

Low

0 (reference)

High

16

Figure 19. Simplified Circuit Diagram

RF INPUT AND OUTPUT

Both RF ports (ATTIN and ATTOUT) are DC-coupled to 0 V. No DC

blocking is required at the RF ports when the RF line potential is

equal to 0 V.

The RF ports are internally matched to 50 Ω. Therefore, external

matching components are not required.

The ADRF5715 supports bidirectional operation at the same power

level. The power handling of the ATTIN and ATTOUT ports are the

same. Refer to the RF power handling specifications in Table 1.

The ADRF5715 can operate with a single positive supply voltage

applied to the VDD pin, and the VSS pin connected to ground.

However, some performance degradations can occur in the input

compression and input third-order intercept (see Table 2).

POWER SUPPLY

The ADRF5715 requires a positive supply voltage applied to the

VDD pin and a negative supply voltage applied to the VSS pin.

Bypassing capacitors are recommended on the supply lines to filter

high frequency noise.

The ideal power-up sequence is as follows:

1. Connect GND.

2. Power up VDD and VSS. Power up VSS after VDD to avoid

current transients on VDD during ramp up.

3. Apply the digital control input. However, powering the digital

control input before the VDD supply can inadvertently forward

bias and damage the internal ESD protection structures. To

avoid this damage, use a series 1 kΩ resistor to limit the current

flowing into the control pin (D0). Use pull-up or pull-down

resistors if the controller output is in a high impedance state

after VDD is powered up and the D0 is not driven to a valid

logic state.

4. Apply an RF input signal to ATTIN or ATTOUT.

The ideal power-down sequence is the reverse order of the power-

up sequence.