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Zakładka z wyszukiwarką danych komponentów |
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Zakładka z wyszukiwarką danych komponentów |
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ADUCM320BBCZ Arkusz danych(PDF) 12 Page - Analog Devices |
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ADUCM320BBCZ Arkusz danych(HTML) 12 Page - Analog Devices |
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12 / 31 page  Data Sheet ADuCM320 Rev. C | Page 11 of 30 Parameter Symbol Min Typ Max Unit Test Conditions/Comments Leakage Current AIN0 to AIN4, AIN6 to AIN15 ±1.5 nA AIN5 ±20 nA Pin shared with comparator Input Current ±9 μA/V At 1 MSPS; buffer off ±6 μA/V ≤800 kSPS; buffer off ±4 μA/V 500 kSPS; buffer off; ADCCNVC[25:16] = 0x1E Input Capacitance 20 pF During ADC acquisition ADC INPUT BUFFER2 When enabled by software Voltage Compliance1 0.15 2.5 V Reduced accuracy below 0.15 V Input Current ±100 nA VIN = 0.15 V to 2.5 V, ADC converting ON-CHIP VOLTAGE REFERENCE 2.51 V 0.47 μF from VREF_1V2 to AGND4; reference is measured with all ADCs, VDACs, and IDACs enabled Accuracy ±5 mV TA = 25°C Reference Temperature Coefficient1 −34 −15 +4 ppm/°C Power Supply Rejection Ratio PSRR 60 dB Internal VREF Power-On Time 50 ms EXTERNAL REFERENCE INPUT Range1 1.8 2.5 V ADC Input Current 200 μA BUFFERED REFFERNCE OUTPUT Output Voltage 2.504 V Accuracy ±8 mV TA = 25°C, load = 1.2 mA Reference Temperature Coefficient1 −55 −5 +40 μV/°C 100 nF from BUF_VREF2V5 to AGND4 Output Impedance 10 Ω TA = 25°C Load Current1 1.2 mA VDAC CHANNEL SPECIFICATIONS RL = 5 kΩ, CL = 100 pF3 DC Accuracy1 12 Bits 1 LSB = 2.5 V/212 Resolution1 12 Bits Number of data bits Relative Accuracy4 INL ±4 LSB 1 LSB = 2.5 V/212 Differential Nonlinearity4 DNL −0.99 +1 LSB Guaranteed monotonic, 1 LSB = 2.5 V/212 Offset Error ±3 ±15 mV 2.5 V internal reference, DAC Output Code 0 Drift ±13 μV/°C Gain Error5 ±0.3 ±0.85 % 0 V to internal VREF range ±0.4 ±1 % 0 V to AVDD range Drift 6.5 ppm/°C Excluding reference drift Mismatch 0.1 % % of full scale on DAC0 Analog Outputs Output Voltage Range 11 0.15 2.5 V Output Voltage Range 21 0.15 AVDDx− 0.15 V Output Impedance 2 Ω DAC AC Characteristics Output Settling Time 10 μs Settled to ±1 LSB Glitch Energy ±20 nV-sec 1 LSB change when the maximum number of bits changes simultaneously in the DACxDAT register IDAC CHANNEL SPECIFICATIONS Resolution1 14 Bits Combination of overlapping 11 bits and 5 bits Full-Scale Output1 150 mA Supply Voltage Each Channel1 1.8 2.5 V Separate PVDDx supply for each channel Output Compliance Range IDAC0, IDAC1 0.4 PVDDx − 400 mV V See Figure 11 IDAC2, IDAC3 0.4 PVDDx − 250 mV V See Figure 11 |
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