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74LVC595AD Arkusz danych(PDF) 10 Page - Nexperia B.V. All rights reserved |
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74LVC595AD Arkusz danych(HTML) 10 Page - Nexperia B.V. All rights reserved |
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10 / 20 page ![]() © Nexperia B.V. 2017. All rights reserved 74LVC595A All information provided in this document is subject to legal disclaimers. Product data sheet Rev. 2 — 20 June 2014 10 of 20 Nexperia 74LVC595A 8-bit serial-in/serial-out or parallel-out shift register; 3-state 12. Waveforms Measurement points are given in Table 8. VOL and VOH are typical output voltage drops that occur with the output load. Fig 7. The shift clock (SHCP) to serial data output (Q7S) propagation delays, the shift clock pulse width and maximum shift clock frequency Measurement points are given in Table 8. VOL and VOH are typical output voltage drops that occur with the output load. Fig 8. The storage clock (STCP) to parallel data output (Qn) propagation delays, the storage clock pulse width and the shift clock to storage clock set-up time |
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