NRF52810-QCAA-R datasheet(96/483 Pages) NORDIC

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Peripherals

Events can be generated by the peripheral even when the event register is set to '1'.

6.1.7 Shortcuts

A shortcut is a direct connection between an event and a task within the same peripheral. If a shortcut is

enabled, its associated task is automatically triggered when its associated event is generated.

Using a shortcut is the equivalent to making the same connection outside the peripheral and through the

PPI. However, the propagation delay through the shortcut is usually shorter than the propagation delay

through the PPI.

Shortcuts are predefined, which means their connections cannot be configured by firmware. Each shortcut

can be individually enabled or disabled through the shortcut register, one bit per shortcut, giving a

maximum of 32 shortcuts for each peripheral.

6.1.8 Interrupts

All peripherals support interrupts. Interrupts are generated by events.

A peripheral only occupies one interrupt, and the interrupt number follows the peripheral ID. For example,

the peripheral with ID=4 is connected to interrupt number 4 in the Nested Vectored Interrupt Controller

(NVIC).

Using the INTEN, INTENSET and INTENCLR registers, every event generated by a peripheral can be

configured to generate that peripheral’s interrupt. Multiple events can be enabled to generate interrupts

simultaneously. To resolve the correct interrupt source, the event registers in the event group of

peripheral registers will indicate the source.

Some peripherals implement only INTENSET and INTENCLR, and the INTEN register is not available on

those peripherals. Refer to the individual chapters for details. In all cases, however, reading back the

INTENSET or INTENCLR register returns the same information as in INTEN.

Each event implemented in the peripheral is associated with a specific bit position in the INTEN, INTENSET

and INTENCLR registers.

The relationship between tasks, events, shortcuts, and interrupts is shown in Tasks, events, shortcuts, and

interrupts on page 94.

Interrupt clearing

When clearing an interrupt by writing "0" to an event register, or disabling an interrupt using the

INTENCLR register, it can take up to four CPU clock cycles to take effect. This means that an interrupt may

reoccur immediatelly even if a new event has not come, if the program exits an interrupt handler after the

interrupt is cleared or disabled, but before four clock cycles have passed.

Important: To avoid an interrupt reoccurring before a new event has come, the program should

perform a read from one of the peripheral registers, for example, the event register that has been

cleared, or the INTENCLR register that has been used to disable the interrupt.

This will cause a one to three-cycle delay and ensure the interrupt is cleared before exiting the interrupt

handler. Care should be taken to ensure the compiler does not remove the read operation as an

optimization. If the program can guarantee a four-cycle delay after event clear or interrupt disable another

way, then a read of a register is not required.

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NRF52810-QCAA-R Arkusz danych(PDF) 96 Page - Nordic Semiconductor