MDT10F6301

This specification is subject to be changed without notice. Please visit our web site for the most updated information.

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P.2

2008/4

Ver. 1.0

5. Order Information

Device

ROM

(Words)

RAM

(Bytes)

EEPROM

(Bytes)

I/O

Comparators

Timer

(8/16 bit)

Package

Remark

MDT10F6301P11

2.0K

96

128

14

1

1/1

16-DIP Pin 5 is PA3 function

MDT10F6301P13

2.0K

96

128

13

1

1/1

16-DIP

Pin 5 is /MCLR

external reset

function

MDT10F6301S11

2.0K

96

128

14

1

1/1

16-SOP Pin 5 is PA3 function

MDT10F6301S13

2.0K

96

128

13

1

1/1

16-SOP

Pin 5 is /MCLR

external reset

function

6. Block Diagram

Stack Eight

Levels

Program

Counters

Oscillator

circuit

Flash ROM

2048 ×14

Instruction

Register

Instruction

Decoder

Working Register

ALU

EEPROM

128×8

Special

Register

Control

Circuit

Status Register

Port A

Port C

Data

8bit

8 bits

11 bits

14 bits

D0~D7

PA0~PA2

PA4~PA5

5 bits

RAM

96 ×8

TMR1

16 Bits

PC0~PC7

8 bits

Comparator

TMR0

8 Bits

PA3

Power on Reset

Watchdog Timer

Power Down Reset