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PSD413A1 Arkusz danych(PDF) 92 Page - STMicroelectronics |
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PSD413A1 Arkusz danych(HTML) 92 Page - STMicroelectronics |
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92 / 123 page  PSD4XX Family 89 -20 -25 ZPLD_TURBO Symbol Parameter Conditions Min Max Min Max OFF * Unit I/O Input or Feedback to tPD Combinatorial Output Port B, E 55 80 Add 20 ns tRPD Registered Input to (Note 1) 55 85 Add 20 ns Combinatorial Output tEA Input to Output Enable Any Input 50 80 Add 20 ns tER Input to Output Disable Any Input 50 80 Add 20 ns tARP Register Clear or Preset Delay Any Input 55 80 Add 20 ns tARPW Register Clear or Preset Any Input 30 60 ns Pulse Width tARD Array Delay 33 35 ns Combinatorial Delays (3.0 V ± 10%) 13.10 AC/DC Parameters – ZPLD Timing Parameters (ZPSD4XXV Versions) (3.0 V ± 10%) NOTE: 1. Port A and latched address from ADIO (A0, A1, A8 – A15). -20 -25 ZPLD_TURBO Symbol Parameter Conditions Min Max Min Max OFF * Unit Maximum Frequency External Feedback 1/(tS + tCO) 28.57 11.11 MHz Maximum Frequency fMAX Internal Feedback (fCNT) 1/(tS+tCO–10) 17.24 12.50 MHz Maximum Frequency Pipelined Data 1/(tCH + tCL) 31.25 18.52 MHz t S Input Setup Time Any Input 45 60 Add 20 ns t H Input Hold Time Any Input 0 0 0 ns t CH Clock High Time Clock Input 16 27 0 ns t CL Clock Low Time Clock Input 16 27 0 ns t CO Clock to Output Delay Clock Input 30 33 0 ns tARD Array Delay for Product Term Expansion Any Macrocell 24 35 0 ns tMIN Minimum Clock Period t CH + t CL 30 30 0 ns Synchronous Clock Mode (3.0 V ± 10%) *NOTE: If ZPLD_TURBO is off and the ZPLD is operating above 15 MHz, there is no need to add 20 ns to the timing parameters. |
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