ST6369 datasheet(22/71 Pages) STMICROELECTRONICS

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INTERRUPT (Continued)

TIMER 2 Interrupt (#1). The TIMER 2 Interrupt is

connectedto the interrupt #1 (0FF6H). The TIMER 2

interrupt generates a low level (which is latched in

the timer). Only the low level selection for #1 can be

used. Bit 6 of the interrupt option register C8H has to

be set.

VSYNC Interrupt (#2). The VSYNC Interrupt is

connected to the interrupt #2. When disabled the

VSYNC INT signal is low. The VSYNC INT signal

is inverted with respect to the signal applied to the

VSYNC pin. Bit 5 of the interrupt option register

C8H is used to select the negative edge (ES2=0)

or the positive edge (ES2=1); the edge will de-

pend on the application. Note that once an edge

has been latched, then the only way to remove

the latched signal is to service the interrupt. Care

must be taken not to generate spurious inter-

rupts. This interrupt may be used for synchronize

to the VSYNC signal in order to change characters

in the OSD only when the screen is on vertical

blanking (if desired). This method may also be

used to blink characters.

TIMER 1 Interrupt (#3). The TIMER 1 Interrupt is

connected to the fourth interrupt #3 (0FF2H) which

detects a low level (latched in the timer).

PWR Interrupt (#4). The PWR Interrupt is con-

nected to the fifth interrupt #4 (0FF0H). If the

PWRINT is disabled at the PWR circuitry, then it

will be high. The #4 interrupt input detects a low

level. A simple latch is provided from the PC4

(PWRIN)pin in order to generate the PWRINT sig-

nal. This latch can be triggered by either the posi-

tive or negative edge of the

PWRIN

signal.

PWRINT is inverted with respect to the latch. The

latch can be reset by software.

Notes Global disable does not reset edge sensi-

tive interrupt flags. These edge sensitive interrupts

become pending again when global disabling is re-

leased. Moreover, edge sensitive interrupts are

stored in the related flags also when interrupts are

globally disabled, unless each edge sensitive inter-

rupt is also individually disabled before the inter-

rupting event happens. Global disable is done by

clearing the GEN bit of Interrupt option register,

while any individual disable is done in the control

ripherals have an interrupt requestflag bit (TMZ), this

bit is set to one when the device wants to generate an

interrupt request and a mask bit (ETI) that must be set

to one to allow the transfer of the flag bit to the Core.

ST6369

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