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ST7SCR1R4T1 Arkusz danych(PDF) 49 Page - STMicroelectronics |
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ST7SCR1R4T1 Arkusz danych(HTML) 49 Page - STMicroelectronics |
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49 / 102 page ![]() ST7SCR 49/102 USB INTERFACE (Cont’d) ENDPOINT 0 REGISTER (EP0R) Read/Write Reset value: 0000 0000(00h) This register is used for controlling Endpoint 0. Bits 6:4 and bits 2:0 are also reset by a USB reset, either received from the USB or forced through the FRES bit in USBCTLR. Bit 7 = CTR0 Correct Transfer. This bit is set by hardware when a correct transfer operation is performed on Endpoint 0. This bit must be cleared after the corresponding interrupt has been serviced. 0: No CTR on Endpoint 0 1: Correct transfer on Endpoint 0 Bit 6 = DTOG_TX Data Toggle, for transmission transfers. It contains the required value of the toggle bit (0=DATA0, 1=DATA1) for the next transmitted data packet. This bit is set by hardware on recep- tion of a SETUP PID. DTOG_TX toggles only when the transmitter has received the ACK signal from the USB host. DTOG_TX and also DTOG_RX are normally updated by hardware, on receipt of a relevant PID. They can be also written by the user, both for testing purposes and to force a specific (DATA0 or DATA1) token. Bits 5:4 = STAT_TX [1:0] Status bits, for transmis- sion transfers. These bits contain the information about the end- point status, which are listed below Table 15. Transmission Status Encoding These bits are written by software. Hardware sets the STAT_TX and STAT_RX bits to NAK when a correct transfer has occurred (CTR=1) addressed to this endpoint; this allows software to prepare the next set of data to be transmitted. Bit 3 = Reserved, forced by hardware to 0. Bit 2 = DTOG_RX Data Toggle, for reception transfers. It contains the expected value of the toggle bit (0=DATA0, 1=DATA1) for the next data packet. This bit is cleared by hardware in the first stage (Setup Stage) of a control transfer (SETUP trans- actions start always with DATA0 PID). The receiv- er toggles DTOG_RX only if it receives a correct data packet and the packet’s data PID matches the receiver sequence bit. 70 CTR0 DTOG _TX STAT_ TX1 STAT_ TX0 0 DTOG _RX STAT_ RX1 STAT_ RX0 STAT_TX1 STAT_TX0 Meaning 00 DISABLED: no function can be executed on this endpoint and messages related to this end- point are ignored. 01 STALL: the endpoint is stalled and all transmission requests result in a STALL handshake. 10 NAK: the endpoint is NAKed and all transmission requests result in a NAK handshake. 11 VALID: this endpoint is enabled (if an address match occurs, the USB interface handles the transaction). 1 |
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