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ST92F120 - INTERRUPTS

5.10 INTERRUPT REGISTERS

CENTRAL INTERRUPT CONTROL REGISTER

(CICR)

R230 - Read/Write

Reset value: 1000 0111 (87h)

Bit 7 = GCEN:

Global Counter Enable.

This bit enables the 16-bit Multifunction Timer pe-

ripheral.

0: MFT disabled

1: MFT enabled

Bit 6 = TLIP:

Top Level Interrupt Pending.

This bit is set by hardware when Top Level Inter-

rupt (TLI) trigger event occurs. It is cleared by

hardware when a TLI is acknowledged. It can also

be set by software to implement a software TLI.

0: No TLI pending

1: TLI pending

Bit 5 = TLI:

Top Level Interrupt.

This bit is set and cleared by software.

0: A Top Level Interrupt is generared when TLIP is

set, only if TLNM=1 in the NICR register (inde-

pendently of the value of the IEN bit).

1: A Top Level Interrupt request is generated when

IEN=1 and the TLIP bit are set.

Bit 4 = IEN:

Interrupt Enable.

This bit is cleared by the interrupt machine cycle

(except for a TLI).

It is set by the iret instruction (except for a return

from TLI).

It is set by the EI instruction.

It is cleared by the DI instruction.

0: Maskable interrupts disabled

1: Maskable Interrupts enabled

Note: The IEN bit can also be changed by soft-

ware using any instruction that operates on regis-

ter CICR, however in this case, take care to avoid

spurious interrupts, since IEN cannot be cleared in

the middle of an interrupt arbitration. Only modify

the IEN bit when interrupts are disabled or when

no peripheral can generate interrupts. For exam-

ple, if the state of IEN is not known in advance,

and its value must be restored from a previous

push of CICR on the stack, use the sequence DI;

POP CICR

to make sure that no interrupts are be-

ing arbitrated when CICR is modified.

Bit 3 = IAM:

Interrupt Arbitration Mode.

This bit is set and cleared by software.

0: Concurrent Mode

1: Nested Mode

Bit 2:0 = CPL[2:0]:

Current Priority Level.

These bits define the Current Priority Level.

CPL=0 is the highest priority. CPL=7 is the lowest

priority. These bits may be modified directly by the

interrupt hardware when Nested Interrupt Mode is

used.

EXTERNAL INTERRUPT TRIGGER REGISTER

(EITR)

R242 - Read/Write

Reset value: 0000 0000 (00h)

Bit 7 = TED1:

INTD1 Trigger Event

Bit 6 = TED0:

INTD0 Trigger Event

Bit 5 = TEC1:

INTC1 Trigger Event

Bit 4 = TEC0:

INTC0 Trigger Event

Bit 3 = TEB1:

INTB1 Trigger Event

Bit 2 = TEB0:

INTB0 Trigger Event

Bit 1 = TEA1:

INTA1 Trigger Event

Bit 0 = TEA0:

INTA0 Trigger Event

These bits are set and cleared by software.

0: Select falling edge as interrupt trigger event

1: Select rising edge as interrupt trigger event

GCEN TLIP

TLI

IEN

IAM

CPL2 CPL1 CPL0

TED1 TED0 TEC1 TEC0 TEB1 TEB0 TEA1 TEA0

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