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STA120

Table 1. Normal Audio Port Modes (M3 = 0)

Special Modes (M3 = 1)

When M3 is high, the special audio modes described in Table 2 are selected via M2, M1, and M0. In for-

mats 8, 9, and 10, SCK, FSYNC, and SDATA are the same as in formats 0, 1, and 2 respectively; however,

the recovered data is output as is even if ERF is high, indicating an error. (In modes 0-2 the previous valid

sample is output).

When out of lock invalid data are sent to the output and the ERF pin goes high.

Format 11 is similar to format 0 except that SCK is an input and FSYNC is an output.

In this mode FSYNC and SDATA are synchronized to the incoming SCK, This mode may be useful when

writing data to storage.

Table 2. Special Audio Port Modes (M3 = 1)

Format 12 is similar to format 7 except that SDATA is the entire data word received from the transmission

line including the C, U, V, and P bits, with zeros in place of the preamble. In format 13 SDATA contains

the entire biphase encoded data from the transmission line including the preamble, and SCK is twice the

normal frequency.

The normal two frame delay of data from input to output is reduced to only a few bit periods in formats 12

and 13. However, the C, U, V bits and error codes follow their normal pathways and therefore follow the

output data by nearly two frames. Figure 4.... illustrates formats 12 and 13. Format 14 is reserved and not

presently used, and format 15 causes the STA120 to go into a reset state. While in reset all outputs will

be inactive except MCK. The STA120 incorporates a Power-on Reset to avoid a Reset at power-up.

C, U, VERF, ERF, and CBL Serial Outputs

The C and U bits and CBL are output one SCK period prior to the active edge of FSYNC in all serial port

formats except 2, 3 and 10 (I

externally. In formats 2, 3 and 10, the C and U bits and CBL are updated with the active edge of FSYNC.

The validity + error flag (VERF) and the error flag (ERF) are always updated at the active edge of FSYNC.

M2

M1

M0

Format

0

0

0

0 - Out, L/R, 16-24 Bits

0

0

1

1 - In, L/R, 16-24 Bits

01

0

01

1

1

0

0

4 - Out, WSYNC, 16-24 Bits

1

0

1

5 - Out, L/R, 16 Bits LSBJ

1

1

0

6 - Out, L/R, 18 Bits LSBJ

1

1

1

7 - Out, L/R, MSB Last

M2

M1

M0

Format

0

0

0

8 - Format 0 - No repeat on error

0

0

1

9 - Format 1 - No repeat on error

0

1

0

10 - Format 2 - No repeat on error

0

1

1

11 - Format 0 - Async. SCK input

1

0

0

12 - Received NRZ Data

1

0

1

13 - Received Bi-phase Data

1

1

0

14 - Reserved

1

1

1

15 - STA120 Reset