AT45DB021B datasheet(14/33 Pages) ATMEL

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AT45DB021B

1937F–DFLSH–10/02

Input Test Waveforms

and Measurement

Levels

tR,tF < 3 ns (10% to 90%)

Output Test Load

AC Waveforms

Two different timing diagrams are shown below. Waveform 1 shows the SCK signal

being low when CS makes a high-to-low transition, and Waveform 2 shows the SCK sig-

nal being high when CS makes a high-to-low transition. Both waveforms show valid

timing diagrams. The setup and hold times for the SI signal are referenced to the low-to-

high transition on the SCK signal.

Waveform 1 shows timing that is also compatible with SPI Mode 0, and Waveform 2

shows timing that is compatible with SPI Mode 3.

Waveform 1 – Inactive

Clock Polarity Low and

SPI Mode 0

Waveform 2 – Inactive

ClockPolarityHighand

SPI Mode 3

DRIVING

LEVELS

MEASUREMENT

LEVEL

0.45V

2.0

0.8

2.4V

DEVICE

UNDER

TEST

30 pF

SCK

tCSS

VALID IN

tSU

tWH

tWL

tCSH

tCS

HIGH IMPEDANCE

VALID OUT

tHO

tDIS

HIGH IMPEDANCE

SCK

tCSS

VALID IN

tSU

tWL

tWH

tCSH

tCS

HIGH Z

VALID OUT

tHO

tDIS

HIGH IMPEDANCE

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