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56F827 Arkusz danych(PDF) 40 Page - Freescale Semiconductor, Inc |
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56F827 Arkusz danych(HTML) 40 Page - Freescale Semiconductor, Inc |
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40 / 60 page ![]() 56F827 Technical Data, Rev. 12 40 Freescale Semiconductor Figure 3-20 SPI Master Timing (CPHA = 0) Figure 3-21 SPI Master Timing (CPHA = 1) SCLK (CPOL = 0) (Output) SCLK (CPOL = 1) (Output) MISO (Input) MOSI (Output) MSB in Bits 14–1 LSB in Master MSB out Bits 14–1 Master LSB out SS (Input) SS is held High on master tR tF tF tDI tDS tDI(ref) tDV tCH tDH tC tR tF tR tCL tCH tCL SCLK (CPOL = 0) (Output) SCLK (CPOL = 1) (Output) MISO (Input) MOSI (Output) MSB in Bits 14–1 LSB in Master MSB out Bits 14– 1 Master LSB out SS (Input) SS is held High on master tC tCL tF tDI tDV(ref) tDV tR tDH tDS tR tCH tCH tCL tF tR tF |
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