ADE7566 datasheet(25/136 Pages) AD

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Preliminary Technical Data

ADE7566/ADE7569

Rev. PrA | Page 25 of 136

Table 19. Scratch Pad 1 SFR (SCRATCH1, 0xFB)

Bit No.

Mnemonic

Default

Description

7 to 0

SCRATCH1

Value can be written/read in this register. This value is maintained in all the power-saving modes.

Table 20. Scratch Pad 2 SFR (SCRATCH2, 0xFC)

Bit No.

Mnemonic

Default

Description

7 to 0

SCRATCH2

Value can be written/read in this register. This value is maintained in all the power-saving modes.

Table 21. Scratch Pad 3 SFR (SCRATCH3, 0xFD)

Bit No.

Mnemonic

Default

Description

7 to 0

SCRATCH3

Value can be written/read in this register. This value is maintained in all the power-saving modes.

Table 22. Scratch Pad 4 SFR (SCRATCH4, 0xFE)

Bit No.

Mnemonic

Default

Description

7 to 0

SCRATCH4

Value can be written/read in this register. This value is maintained in all the power-saving modes.

Table 23. Power Control SFR (POWCON, 0xC5)

Bit No.

Mnemonic

Default

Description

RESERVED

Reserved.

METER_OFF

Set this bit to turn off the modulators and energy metering DSP circuitry to reduce power if

metering functions are not needed in PSM0.

RESERVED

Reserved.

COREOFF

Set this bit to shut down the core if in the PSM1 operating mode.

RESERVED

Reserved.

Controls the core clock frequency, fCORE. fCORE = 4.096 MHz/2CD.

CD[2:0]

Result (fCORE in MHz)

000

4.096

001

2.048

010

1.024

011

0.512

100

0.256

101

0.128

110

0.064

2 to 0

CD[2:0]

010

111

0.032

Writing to the Power Control SFR (POWCON, 0xC5)

Writing data to the POWCON SFR involves a double instruction sequence. Global interrupts must first be disabled to ensure that the two

instructions occur consecutively. The Key SFR (KYREG, 0xC1) is set to 0xA7 and is immediately followed by a write to the POWCON SFR.

For example:

CLR EA

;Disable Interrupts while configuring to WDT

MOV KYREG,#0A7h

;Write KYREG to 0xA7 to get write access to the POWCON SFR

MOV POWCON, #10H

;Shutdown the core

NOP

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