IMX27L datasheet(51/122 Pages) FREESCALE

Numer części	IMX27L

Szczegółowy opis	Multimedia Applications

PDF	122 Pages

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Producent	FREESCALE [Freescale Semiconductor, Inc]

Strona internetowa	http://www.freescale.com

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Signal Descriptions

i.MX27/i.MX27L Data Sheet, Advance Information, Rev. 1

Freescale Semiconductor

Preliminary—Subject to Change Without Notice

3.5.5

CMOS Sensor Interface (CSI)

This section describes the electrical information (AC timing) of the CSI.

3.5.5.1

Gated Clock Mode Timing

VSYNC, HSYNC, and PIXCLK signals are used in this mode. A frame starts with a rising/falling edge on

VSYNC, then HSYNC goes high and holds for the entire line. The pixel clock is valid as long as HSYNC

is high. Figure 9 and Figure 10 depict the gated clock mode timings of CSI, and Table 20 lists the timing

parameters.

Figure 9 shows sensor output data on the pixel clock falling edge. The CSI latches data on the pixel clock

rising edge.

Figure 9. CSI Timing Diagram, Gated, PIXCLK—Sensor Data at Falling Edge,

Latch Data at Rising Edge

VSYNC

HSYNC

PIXCLK

DATA[7:0]

Valid Data

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