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CybraTech (2000) Ltd.
SOC-3000/i Scale-On-Chip
ASIC
Technical Specification
.
Revision B
Page 26
July, 2002
In the SOC-3000, the MOVX instruction may take only two machine cycles or eight
oscillator cycles, while the “MOV direct, direct” instruction uses three machine cycles or 12
oscillator cycles. Thus, the execution times of the two instructions differ. This is because the
SOC-3000 usually uses one instruction cycle for each instruction byte.
Note that a machine cycle requires just four clocks, and provides one ALE pulse per cycle.
Many instructions require only one cycle, but some require five.
Reset
The Reset signal is generated by an internal circuitry in the ASIC. The signal thresholds are:
RESET Falling edge on Vcc=3.98V.
RESET Rising edge on Vcc=4.19V.
The hystheresis of the RESET signal is set so that normal operation of the internal Flash
memory is guaranteed.
Interrupt Vectors
The interrupt vectors of the SOC-3000/I are shifted compared with the interrupt vectors of a
standard 80C51TBO vectors by an offset of 1000H.
Table 6 details the SOC-3000/I interrupt vectors:
TABLE 6:
INTERRUPT VECTORS DESCRIPTION
INTERRUPT SOURCE
FLAG
VECTOR
LOCATION
PRIORITY
External Interrupt 0
IE0
1003H
1 (Highest)
Timer 0 Overflow
TF0
100BH
2
External Interrupt 1
IE1
1013H
3
Timer 1 Overflow
TF1
101BH
4
Serial Port
RI + TI
1023H
5
Timer 2 Overflow
TF2 + EXF2
102BH
6
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