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STOTG04ES Arkusz danych(PDF) 4 Page - STMicroelectronics |
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STOTG04ES Arkusz danych(HTML) 4 Page - STMicroelectronics |
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4 / 26 page ![]() Pin configuration STOTG04ES 4/26 (1) Input and open-drain output (2) Input with internal pull-up resistor (3) Internal regulator can be bypassed by connecting VBAT to this pin when the VBAT is in range of 2.7V to 3.6V Figure 2. Functional diagram 23 CGND Power Ground for the charge pump 24 VIF Power Logic power supply (+1.6V to 3.6V) PlN N° SYMBOL I/O NAME AND FUNCTION |
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