STLC1PD datasheet(6/16 Pages) STMICROELECTRONICS

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STLC1

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ELECTRICAL CHARACTERISTICS FOR FEEDBACK AND CONTROL (TJ=-40 to 125°C unless

otherwise specified. Typical values are referred at TJ=25°C, VB+=14V)

Note 1: The device is powered. If only one of the three inputs is enabled (the remaining inputs are shorted to ground), tSMPS-ON is the time

required for the OUT voltage to reach the10% of its own steady state value

Note 2: The device is powered. If only one of the three inputs is brought high (the remaining inputs are shorted to ground), TLSD-ON is the

time required for the current to flow in the enabled LSD

Note 3: The device is powered and at least one input is enabled. If this input is disabled, TLSD-OFF is the time required for the current to be-

come zero in the previously enabled LSD.

Note 4: Guaranteed by design, not tested in production.

FUNCTIONAL DESCRIPTION

SMPS

The

N-channel

Power

MOSFET

source

grounded, thus it is possible to use any converter

configuration with the power switch connected to

ground. A SEPIC topology (Single Ended Primary

Inductor

Current)

shown

the

typical

application schematic.

INPUTS PINS

The IC’s inputs are TURN, STOP and TAIL. If all

inputs are disabled, SMPS and most of the

internal control and diagnostic circuitry are not

active. This is done in order to maintain the

stand-by quiescent current at very low values.

When only one of these inputs is put high (e.g

connected to VB+), a device start-up phase

begins. First the CREF capacitor is charged and,

once the voltage on it has reached about 95% of

its steady state value (VREF), the SMPS is

enabled. In order to allow the output to reach the

regulated

voltage

value

faster,

the

LSD

corresponding to the input enabled will conduct

Symbol

Parameter

Test Conditions

Min.

Typ.

Max.

Unit

VLOUT

Lamp Outage Detect

Threshold Voltage

TJ=25°C

150

200

250

VH-SHORT Output Overcurrent

Threshold Voltage

TJ=25°C

1.2

1.3

1.6

VREF

External Voltage

Reference

VTURN =VSTOP =VTAIL =VB+

IREF =500µA

3.6

3.8

VFB

Internal Band-gap Voltage

Reference (see schematic

diagram)

VTURN =VSTOP =VTAIL =VB+

1.15

1.24

1.3

VLH(en)

Device Enabled Lamp

Outage no fault High

Voltage

VB+ = 9 to 16V, ILMP-OUT <-4mA

least one input enabled. No fault

condition.

VB+-2

VB+

VLH(dis)

Device Disabled Lamp

Outage no fault High

Voltage

VB+ = 9 to 16V, ILMP-OUT <-2mA

VTURN =VSTOP =VTAIL =0V

VB+-2

VB+

VLL

Lamp Outage fault Low

Voltage

VB+ = 9 to 16V ILMP-OUT < 100mA At

least one input enabled. Fault condition.

1.5

R(IN)

TURN, STOP and TAIL

Input Resistance

VB+ = 12V,

18.5

Ω

TSHDN

Thermal Shutdown

Threshold

(see Note 4)

150

°C

THYST

Thermal Shutdown

Hysteresis

(see Note 4)

°C

tF(on)

Time to Fault Indication

µs

tF(off)

Time to Fault Indication

OFF

8ms

VTS-PWM(L) TS-PWM Low State

Voltage (see table 1)

0.1VREF

VTS-PWM(M) TS-PWM Mid State

Voltage (see table 1)

0.21VREF

0.79VREF

VTS-PWM(H) TS-PWM High State

Voltage (see table 1)

0.98VREF

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