KBMF datasheet(3/8 Pages) STMICROELECTRONICS

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2. ESD PROTECTION

The KBMFxxSC6 is particularly optimized to perform ESD protection. ESD protection is based on the use

of device which clamps at:

Voutput = VBR + Rd.IPP

This protection function is splitted in 2 stages. As shown in figure 4, the ESD strikes are clamped by the

first stage S1 and then its remaining overvoltage is applied to the second stage through the resistor R.

Such a configuration makes the output voltage very low at the Voutput level.

To have a good approximation of the remaining voltages at both Vinput and Voutput stages, we give the

typical dynamical resistance value Rd. By taking into account these following hypothesis : Rt>Rd, Rg>Rd

and Rload>Rd, it gives these formulas:

The results of the calculation done for VPP=8kV, Rg=330Ω (IEC 61000-4-2 standard), VBR=7V (typ.) and

Rd = 1Ω (typ.) give:

Vinput = 31.2 V

Voutput = 7.8 V

This confirms the very low remaining voltage across the device to be protected. It is also important to note

that in this approximation the parasitic inductance effect was not taken into account. This could be few

tenths of volts during few ns at the input side. This parasitic effect is not present at the output side due the

low current involved after the resistance RS.

The measurements done here after show very clearly (figure 6) the high efficiency of the ESD protection :

- no influence of the parasitic inductances on output stage

- Voutput clamping voltage very close to VBR (positive strike) and -VF (negative strike)

Figure 4: ESD clamping behavior

ESD Surge

Vinput

Voutput

Rload

Device

to be

protected

KBMFxxSC6

input

⋅

------------------------------------------------------

output

input

⋅

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