ADP2503ACPZ-4.2-R71 datasheet(14/16 Pages) AD

14 / 16 page

ADP2503/ADP2504

Preliminary Technical Data

PCB LAYOUT GUIDELINES

Poor layout can affect ADP2503/ADP2504 performance,

causing electromagnetic interference (EMI) and electromagnetic

compatibility (EMC) performance, ground bounce, and voltage

losses. Poor layout can also affect regulation and stability. A

good layout is implemented using the following rules:

• Place the inductor, input capacitor, and output capacitor

close to the IC using short tracks. These components carry

high switching frequencies and large tracks act like

antennas.

• Route the output voltage path away from the inductor and

SW node to minimize noise and magnetic interference.

• Maximize the size of ground metal on the component side

to help with thermal dissipation.

• Use a ground plane with several vias connecting to the

component side ground to further reduce noise interference

on sensitive circuit nodes.

VIN

PGND

VOUT

PGND

TP1

TP2

10mm

8mm

JP1

SYNC

ADP2503/ADP2504 EVALUATION BOARD

Figure 28. ADP2503/ADP2504 Evaluation Board

Rev. PrB | Page 14 of 16

ADP2503ACPZ-4.2-R71 Arkusz danych(PDF) 14 Page - Analog Devices