L6756D datasheet(23/36 Pages) STMICROELECTRONICS

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L6756D

Output voltage positioning

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5.5

Dynamic VID transitions

L6756D manages dynamic VID transitions that allow the output voltage to modify during

normal device operation for CPU power management purposes. OV and UV signals are

properly masked during every DVID Transition and they are re-activated with a 16 clock

cycle delay to prevent from false triggering.

When changing dynamically the regulated voltage (DVID), the system needs to charge or

discharge the output capacitor accordingly. This means that an extra-current IDVID needs to

be delivered (especially when increasing the output regulated voltage) and it must be con-

sidered when setting the over current threshold of both the sections. This current results:

where dVOUT / dTVID depends on the operative mode (typically externally driven).

Dynamic VID transition is managed by checking for VID code modifications (See Figure 8)

on the rising edge of an internal additional DVID-clock and waiting for a confirmation on the

following falling edge. Once the new code is stable, on the next rising edge, the reference

starts stepping up or down in LSB increments every two DVID-clock cycle until the new VID

code is reached.

DVID-clock frequency (FDVID) is 1 MHz (Typ).

Caution:

Overcoming the OC threshold during the DVID causes the device latch and disable.

Caution:

If the new VID code is more than 1 LSB different from the previous, the device will execute

the transition stepping the reference with the DVID-clock frequency FDVID until the new code

has reached. The output voltage rate of change will be of [LSB]mV * FDVID!

Figure 8.

DVID transitions

DVID

OUT

VID

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