M24M01-R_08 datasheet(18/36 Pages) STMICROELECTRONICS

18 / 36 page

Device operation

M24M01-R, M24M01-W, M24M01-HR

18/36

3.10

Minimizing system delays by polling on ACK

During the internal Write cycle, the device disconnects itself from the bus, and writes a copy

of the data from its internal latches to the memory cells. The maximum Write time (tw) is

shown in Table 13, but the typical time is shorter. To make use of this, a polling sequence

can be used by the bus master.

The sequence, as shown in Figure 9, is:

●

Initial condition: a Write cycle is in progress.

●

Step 1: the bus master issues a Start condition followed by a device select code (the

first byte of the new instruction).

●

Step 2: if the device is busy with the internal Write cycle, no Ack will be returned and

the bus master goes back to Step 1. If the device has terminated the internal Write

cycle, it responds with an Ack, indicating that the device is ready to receive the second

part of the instruction (the first byte of this instruction having been sent during Step 1).

Figure 10.

Read mode sequences

The seven most significant bits of the device select code of a Random Read (in the 1st and 4th bytes) must

be identical.

Dev sel *

Byte addr

Dev sel

Data out 1

AI01105d

Data out N

Current

Address

Read

Dev sel

Data out

Random

Address

Read

Dev sel *

Data out

Sequential

Current

Read

Data out N

Dev sel *

Byte addr

Sequention

Random

Read

Dev sel *

Data out1

ACK

R/W

NO ACK

ACK

R/W

ACK

R/W

ACK

NO ACK

R/W

NO ACK

ACK

R/W

ACK

R/W

ACK

NO ACK

M24M01-R Arkusz danych(PDF) 18 Page - STMicroelectronics

M24M01-R Arkusz danych(HTML) 18 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36

Arkusz danych Pobierz

Link URL