L5983_08 datasheet(18/37 Pages) STMICROELECTRONICS

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Application information

L5983

18/37

Equation 15

As seen in Chapter 4.3 two different kind of network can compensate the loop. In the two

following paragraph the guidelines to select the Type II and Type III compensation network

are illustrated.

Figure 9.

Error amplifier, PWM modulator and LC output filter

5.4.1

Type III compensation network

The methodology to stabilize the loop consists of placing two zeros to compensate the effect

of the LC double pole, so increasing phase margin; then to place one pole in the origin to

minimize the dc error on regulated output voltage; finally to place other poles far away the

zero dB frequency.

If the equivalent series resistance (ESR) of the output capacitor introduces a zero with a

frequency higher than the desired bandwidth (that is: 2

π * ESR * C

OUT < 1 /BW), the type III

compensation network is needed. Multi Layer Ceramic capacitors (MLCC) have very low

ESR (<1 m

Ω), with very high frequency zero, so type III network is adopted to compensate

the loop.

In Figure 10 the type III compensation network is shown. This network introduces two zeros

(fZ1, fZ2) and three poles (fP0, fP1, fP2). They expression are:

Equation 16

Equation 17

OUT

ESR

()

⋅⋅

⋅

OUT

ESR

⋅⋅

------------------------------------------------------------------------------------------

OUT

--------------

COMP

REF

E/A

PWM

OUT

ESR

PW0

COMP

REF

E/A

PWM

OUT

ESR

PW0

π C

()

⋅⋅

------------------------------------------------

π R

⋅⋅

------------------------------

π R

⋅⋅

------------------------------

π R

⋅

--------------------

⋅⋅

--------------------------------------------

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