33982 datasheet(21/35 Pages) FREESCALE

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Analog Integrated Circuit Device Data

Freescale Semiconductor

33982

FUNCTIONAL DEVICE OPERATION

LOGIC COMMANDS AND REGISTERS

FUNCTIONAL DEVICE OPERATION

LOGIC COMMANDS AND REGISTERS

SPI PROTOCOL DESCRIPTION

The SPI interface has a full duplex, three-wire

synchronous data transfer with four I/O lines associated with

it: Serial Clock (SCLK), Serial Input (SI), Serial Output (SO),

and Chip Select (CS).

The SI/SO pins of the 33982B follow a first-in first-out (D7/

D0) protocol with both input and output words transferring the

most significant bit (MSB) first. All inputs are compatible with

5.0 V CMOS logic levels.

The SPI lines perform the following functions:

SERIAL CLOCK (SCLK)

The SCLK pin clocks the internal shift registers of the

33982B device. The serial input pin (SI) accepts data into the

input shift register on the falling edge of the SCLK signal

while the serial output pin (SO) shifts data information out of

the SO line driver on the rising edge of the SCLK signal. It is

important that the SCLK pin be in a logic LOW state

whenever CS makes any transition. For this reason, it is

recommended that the SCLK pin be in a Logic [0] state

whenever the device is not accessed (CS Logic [1] state).

SCLK has an active internal pull-down, IDWN. When CS is

Logic [1], signals at the SCLK and SI pins are ignored and SO

is tri-stated (high-impedance). (See Figure 10 and

Figure 11.)

SERIAL INTERFACE (SI)

This is a serial interface (SI) command data input pin. SI

instruction is read on the falling edge of SCLK. An 8-bit

stream of serial data is required on the SI pin, starting with D7

to D0. The internal registers of the 33982B are configured

and controlled using a 4-bit addressing scheme, as shown in

Table 8. Register addressing and configuration are described

in Table 9. The SI input has an active internal pull-down,

IDWN.

SERIAL OUTPUT (SO)

The SO pin is a tri-stateable output from the shift register.

The SO pin remains in a high-impedance state until the CS

pin is put into a Logic [0] state. The SO data is capable of

reporting the status of the output, the device configuration,

and the state of the key inputs. The SO pin changes states on

the rising edge of SCLK and reads out on the falling edge of

SCLK. Fault and input status descriptions are provided in

Table 15.

CHIP SELECT (CS)

The CS pin enables communication with the master

microcontroller (MCU). When this pin is in a Logic [0] state,

the device is capable of transferring information to and

receiving information from the MCU. The 33982B latches in

data from the input shift registers to the addressed registers

on the rising edge of CS. The device transfers status

information from the power output to the shift register on the

falling edge of CS. The SO output driver is enabled when CS

is Logic [0]. CS should transition from a Logic [1] to a Logic [0]

state only when SCLK is a Logic [0]. CS has an active internal

pull-up, IUP.

Figure 10. Single 8-Bit Word SPI Communication

CSB

SCLK

OD7

OD6

OD1

OD2

OD3

OD4

OD5

OD0

RST

1. RST is a Logic [1] state during the above operation.

2. D7:D0 relate to the most recent ordered entry of data into the device.

3. OD7:OD0 relate to the first 8 bits of ordered fault and status data out of the device.

Notes

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