M30624FGPFP datasheet(70/101 Pages) RENESAS

70 / 101 page

M16C/62P Group (M16C/62P, M16C/62PT)

5. Electrical Characteristics

Rev.2.41

Jan 10, 2006

Page 70 of 96

REJ03B0001-0241

VCC1=VCC2=3V

Switching Characteristics

(VCC1 = VCC2 = 3V, VSS = 0V, at Topr =

−20 to 85°C / −40 to 85°C unless otherwise specified)

NOTES:

Calculated according to the BCLK frequency as follows:

f(BCLK) is 12.5MHz or less.

Calculated according to the BCLK frequency as follows:

This standard value shows the timing when the output is off, and

does not show hold time of data bus.

Hold time of data bus varies with capacitor volume and pull-up

(pull-down) resistance value.

Hold time of data bus is expressed in

t =

−CR X ln (1−VOL / VCC2)

by a circuit of the right figure.

For example, when VOL = 0.2VCC2, C = 30pF, R = 1k

Ω, hold time

of output ”L” level is

t =

−30pF X 1k Ω X In(1−0.2VCC2 / VCC2)

= 6.7ns.

Figure 5.12

Ports P0 to P14 Measurement Circuit

Table 5.46

Memory Expansion and Microprocessor Modes (for setting with no wait)

Symbol

Parameter

Standard

Unit

Min.

Max.

td(BCLK-AD)

Address Output Delay Time

See

Figure 5.12

th(BCLK-AD)

Address Output Hold Time (in relation to BCLK)

th(RD-AD)

Address Output Hold Time (in relation to RD)

th(WR-AD)

Address Output Hold Time (in relation to WR)

(NOTE 2)

td(BCLK-CS)

Chip Select Output Delay Time

th(BCLK-CS)

Chip Select Output Hold Time (in relation to BCLK)

td(BCLK-ALE)

ALE Signal Output Delay Time

th(BCLK-ALE)

ALE Signal Output Hold Time

−4ns

td(BCLK-RD)

RD Signal Output Delay Time

th(BCLK-RD)

RD Signal Output Hold Time

td(BCLK-WR)

WR Signal Output Delay Time

th(BCLK-WR)

WR Signal Output Hold Time

td(BCLK-DB)

Data Output Delay Time (in relation to BCLK)

th(BCLK-DB)

Data Output Hold Time (in relation to BCLK) (3)

4ns

td(DB-WR)

Data Output Delay Time (in relation to WR)

(NOTE 1)

th(WR-DB)

Data Output Hold Time (in relation to WR) (3)

(NOTE 2)

td(BCLK-HLDA)

HLDA Output Delay Time

0.5x10

fBCLK

()

------------------------40 ns

[]

–

0.5x10

fBCLK

()

------------------------10 ns

[]

–

DBi

P10

30pF

P11

P12

P13

P14

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