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HD74LS78AFPEL Arkusz danych(PDF) 1 Page - Renesas Technology Corp

Numer części HD74LS78AFPEL
Szczegółowy opis  Dual J-K Flip-Flops (with Preset, Common Clear, and Common Clock)
PDF  7 Pages
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Producent  RENESAS [Renesas Technology Corp]
Strona internetowa  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

HD74LS78AFPEL Arkusz danych(HTML) 1 Page - Renesas Technology Corp

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Rev.3.00, Jul.22.2005, page 1 of 6
HD74LS78A
Dual J-K Flip-Flops
(with Preset, Common Clear, and Common Clock)
REJ03D0419–0300
Rev.3.00
Jul.22.2005
Features
• Ordering Information
Part Name
Package Type
Package Code
(Previous Code)
Package
Abbreviation
Taping Abbreviation
(Quantity)
HD74LS78AFPEL
SOP-14 pin (JEITA)
PRSP0014DF-B
(FP-14DAV)
FP
EL (2,000 pcs/reel)
Note:
Please consult the sales office for the above package availability.
Pin Arrangement
(Top view)
1K
1Q
1
Q
GND
2
Q
2J
CK
2K
1PR
1J
VCC
CLR
2PR
2Q
1
2
3
4
5
6
7
14
8
9
10
11
12
13
CK
PR
CLR
KJ
Q
Q
CK
PR
CLR
KJ
Q
Q
Function Table
Inputs
Outputs
Preset
Clear
Clock
J
K
Q
Q
L
H
X
X
X
H
L
H
L
X
X
X
L
H
L
L
X
X
X
H*
H*
H
H
L
L
Q0
Q
0
H
H
H
L
H
L
H
H
L
H
L
H
H
H
H
H
Toggle
H
H
H
X
X
Q0
Q
0
Notes: H; high level, L; low level, X; irrelevant,
↓; transition from high to low level,
Q0; level of Q before the indicated steady-state input conditions were established.
Q
0; complement of Q0 or level of Q before the indicated steady-state input conditions were established.
Toggle; each output changes to the complement of its previous level on each active transition indicated by
↓.
* This configuration is nonstable; that is, it will not persist when preset and clear inputs return to their inactive (high) level.


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