HD74AC283AFPEL datasheet(2/10 Pages) RENESAS

2 / 10 page

HD74AC283/HD74ACT283

Rev.2.00, Jul.16.2004, page 2 of 9

Logic Symbol

Pin Names

0 – A3

A Operand Inputs

0 – B3

B Operand Inputs

Carry Input

0 – S3

Sum Outputs

Carry Output

Functional Description

The HD74AC283/HD74ACT283 adds two 4-bit binary words (A plus B) plus the incoming Carry (C

0). The binary sum

appears on the Sum (S

0 – S3) and outgoing carry (C4) outputs. The binary weight of the various inputs and outputs is

indicated by the subscript numbers, representing powers of two.

0 (A

0 + B0 + C0) + 2

1 (A

1 + B1) + 2

2 (A

2 + B2) + 2

3 (A

3 + B3) = S0 + 2S1 + 4S2 + 8S3 + 16C4

Where (+) = plus

Interchanging inputs of equal weight does not affect the operation. Thus C

0, A0, B0 can be arbitrarily assigned to pins 5,

6 and 7 for DIPS. Due to the symmetry of the binary add function, the HD74AC283/HD74ACT283 can be used either

with all inputs and outputs active High (positive logic) or with all inputs and outputs active Low (negative logic). See

Figure a. Note that if C

0 is not used it must be tied Low for active High logic or tied High for active Low logic.

Due to pin limitations, the intermediate carries of the HD74AC283/HD74ACT283 are not brought out for use as inputs

or outputs. However, other means can be used to effectively insert a carry into, or bring a carry out from, an

intermediate stage. Figure b shows how to make a 3-bit adder. Tying the operand inputs of the fourth adder (A

3, B3)

Low makes S

3 dependent only on, and equal to, the carry from the third adder. Using somewhat the same principle

Figure c shows a way of dividing the HD74AC283/HD74ACT283 into a 2-bit and a 1-bit adder. The third stage adder

2, B2, S2) is used merely as a means of getting a carry (C10) signal into the fourth stage (via A2 and B2) and bringing

out the carry from the second stage on S

2. Note that as long as A2 and B2 are the same, whether High or Low, they do

not influence S

2. Similarly, when A2 and B2 are the same the carry into the third stage does not influence the carry out

of the third stage. Figure d shows a method of implementing a 5-input encoder, where the inputs are equally weighted.

The outputs S

0, S1 and S2 present a binary number equal to the number of inputs I1 – I5 that are true. Figure e shows one

method of implementing a 5-input majority gate. When three or more of the inputs I

1 – I5 are true, the output M5 is true.

Fig. a Active HIGH varsus Active LOW Interpretation

Logic levels

Active HIGH

00101100

1001

Active LOW

11010011

0110

Active HIGH: 0 + 10 + 9 = 3 + 16

Active LOW: 1 + 5 + 6 = 12 + 0

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