STV9432 datasheet(14/18 Pages) STMICROELECTRONICS

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STV9432

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Capture Process Time Constant (reset value: 24H)

Initial Pixel Period (reset value: 06H)

8.4 - OSD TIMINGS

The number of pixel periods is given by the LINE

DURATION register and is equal to:

[LD[6:1] x 2 + 1 ] x 12.

(LD[6:1]: value of the LINE DURATION register).

This value is used to define the horizontal size of

the characters.

The horizontal left margin is given by the HORI-

ZONTAL DELAY register and is equal to:

(DD[7:0] -6) x 6 + 54

(DD[7:0]: value of the DISPLAY DELAY register).

This value is used to define the horizontal position

of the characters on the screen. Due to internal

logic, minimum horizontal delay is fixed at 4.5

characters (54 pixel) when DD is even and inferior

or equal to 6, and it is fixed at 5 characters (60

pixel) when DD is odd and inferior or equal to 7.

8.5 - PLL

The PLL function of the STV9432 provides the

internal pixel clock locked on the horizontal syn-

chro signal and used by the display processor to

generate the R, G, B and fast blanking signals. It

is made of 2 PLLs. The first PLL which is analog

(see Figure 6) provides a high frequency that is 40

times the internal oscillator frequency, or 320MHz.

This high frequency clock is used by the Display

controller.

The 320MHz frequency is then divided by three.

The resulting 106.7MHz clock is used by the

Video timings analysis block.

The second PLL, fully digital (see Figure 7), pro-

vides a pixel frequency locked on the horizontal

synchro signal. The ratio between the frequencies

of these 2 signals is:

M = 12 x (LD[6:1] x 2 + 1) where LD[6:1] is the

value of the LINE DURATION register.

Figure 6. Analog PLL

Figure 7. Digital PLL

8.5.1 - Programming of the PLL Registers

Initial Pixel Period (@4037)

This register allows to increase the speed of the

PLL convergence when the horizontal frequency

changes (new graphic standard).

The relationship between PP[7:0], LD[6:1], fHSYNC

and fOSC is:

4036

LEN

AF2

AF1

AF0

BF2

BF1

BF0

LEN

Lock enable

0 = R,G,B, FBLK are always enabled,

1 = R,G,B,, FBLK are enabled only when PLL is locked.

AF[2:0]

Phase constant during the capture process.

BF[2:0]

Frequency constant during the capture process.

4037

PP7

PP6

PP5

PP4

PP3

PP2

PP1

PP0

PP[7:0]

Value to initialize the pixel period of the PLL.

VCO

FILTER

N • f

OSC

ALGO

M • f

H-SYNC

err(n)

D(n)

40 • f

OSC

40 .

fOSC

6. (2 . LD + 1) . fHSYNC

PP[7:] = round

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