HD6432351 datasheet(459/1025 Pages) RENESAS

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Section 10 16-Bit Timer Pulse Unit (TPU)

Rev. 3.00 Sep 15, 2006 page 425 of 988

REJ09B0330-0300

10.2.2

Timer Mode Register (TMDR)

—

BFB

R/W

BFA

R/W

MD3

R/W

MD0

R/W

MD2

R/W

MD1

R/W

Bit

Initial value

R/W

Channel 0: TMDR0

Channel 3: TMDR3

—

MD3

R/W

MD0

R/W

MD2

R/W

MD1

R/W

Bit

Initial value

R/W

Channel 1: TMDR1

Channel 2: TMDR2

Channel 4: TMDR4

Channel 5: TMDR5

The TMDR registers are 8-bit readable/writable registers that are used to set the operating mode

for each channel. The TPU has six TMDR registers, one for each channel. The TMDR registers

are initialized to H'C0 by a reset, and in hardware standby mode.

TMDR register settings should be made only when TCNT operation is stopped.

Bits 7 and 6—Reserved: Read-only bits, always read as 1.

Bit 5—Buffer Operation B (BFB): Specifies whether TGRB is to operate in the normal way, or

TGRB and TGRD are to be used together for buffer operation. When TGRD is used as a buffer

In channels 1, 2, 4, and 5, which have no TGRD, bit 5 is reserved. It is always read as 0 and

cannot be modified.

Bit 5

BFB

Description

TGRB operates normally

(Initial value)

TGRB and TGRD used together for buffer operation

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