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H8SX/1663R Arkusz danych(PDF) 189 Page - Renesas Technology Corp |
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H8SX/1663R Arkusz danych(HTML) 189 Page - Renesas Technology Corp |
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189 / 1504 page ![]() Section 7 Interrupt Controller Rev. 2.00 Sep. 24, 2008 Page 157 of 1468 REJ09B0412-0200 7. The CPU generates a vector address for the accepted interrupt and starts execution of the interrupt handling routine at the address indicated by the contents of the vector address in the vector table. Program execution state Interrupt generated? NMI IRQ0 IRQ1 TEI4 I = 0 Save PC and CCR I ← 1 Read vector address Branch to interrupt handling routine Yes No Yes Yes Yes No No No Yes Yes No Pending Figure 7.3 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 0 |
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