H8SXSLASH1663M datasheet(1470/1504 Pages) RENESAS

1470 / 1504 page

Main Revisions and Additions in this Edition

Rev. 2.00 Sep. 24, 2008 Page 1438 of 1468

REJ09B0412-0200

Item

Page

Revision (See Manual for Details)

12.4 Location of Transfer

Information and DTC Vector

Table

Table 12.1 Interrupt Sources,

DTC Vector Addresses, and

Corresponding DTCEs

572

Amended

DTC Vector Address offset of the origin of activation source

for the external pin

EXDMTEND3 H'61C

12.9.3 DMAC Transfer End

Interrupt

592

Added

When the DTC is activated by a DMAC transfer end

interrupt, even if DISEL=0, an automatic clearing of the

relevant activation source flag is not automatically cleared

by the DTC. Therefore, write 1 to the DTE bit by the DTC

transfer and clear the activation source flag to 0.

12.9.9 Points for Caution

when Overwriting DTCER.

594

Added

Section 13 I/O Ports

13.2 Output Buffer Control

13.2.6 Port A

626,

629

Amended

(2) PA6/

AS/AH/BS-B

Setting of the I/O Port

[Before amendment]

BSB_OE →

[After amendment]

BS-B_OE

(7) PA1/

BACK/(RD/WR-A)

Pin function of the bus controller

[Before amendment] RD/

WR output →

[After amendment] RD/

WR-A output

Setting of the I/O Port

[Before amendment] (RD

/WR)_OE →

[After amendment] (RD

/WR) -A_OE

Table 13.5 Available Output

Signals and Settings in Each

Port

653

Replaced

Replaced due to the correction of an error

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