H8SXSLASH1663M datasheet(1475/1504 Pages) RENESAS

1475 / 1504 page

Main Revisions and Additions in this Edition

Rev. 2.00 Sep. 24, 2008 Page 1443 of 1468

REJ09B0412-0200

Item

Page

Revision (See Manual for Details)

1246

Amended

DPSBYCR controls deep software standby mode.

DPSBYCR is not initialized by the internal reset signal upon

exit from deep software standby mode.

1248

Amended

Descriptions for bit 5 in the register table:

On-chip RAM Power Off 2

RAMCUT 2, 1, and 0 control the internal power supply to

the on-chip RAM and USB in deep software standby mode.

For details, see descriptions of the RAMCUT0 bit

Amended

Descriptions for bit 4 in the register table:

On-chip RAM Power Off 1

RAMCUT 2, 1, and 0 control the internal power supply to

the on-chip RAM and USB in deep software standby mode.

For details, see descriptions of the RAMCUT0 bit.

28.2.4 Deep Standby Control

Amended

Descriptions for bit 0 in the register table:

On-chip RAM Power Off 0

RAMCUT 2, 1, and 0 control the internal power supply to

the on-chip RAM and USB in deep software standby

mode. For details, see descriptions of the RAMCUT0 bit.

28.2.5 Deep Standby Wait

Control Register (DPSWCR)

1249

Amended

DPSWCR is not initialized by the internal reset signal upon

exit from deep software standby mode.

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