SH7052 datasheet(9/919 Pages) RENESAS

9 / 919 page

Page

Item

Revisions (See Manual for Details)

562

16.1.3 Pin Configuration

Description amended

570

16.2.3 A/D Control Registers 0

and 1 (ADCR0, ADCR1)

Description amended

585

16.4.4 External Triggering of

A/D Converter

Description amended

600

17.5.3 ROM Area Writes

New description added

701

20.5.5 RAM Emulation Register

(RAMER)

Description of bits 15 to 4 added

The write value should always be 0.

713

20.7.3 Erase Mode

Description amended

722

20.10 Note on Flash Memory

Programming/Erasing

Description added

763

21.7.3 Erase Mode

Description amended

797

23.3.1 Transition to Hardware

Standby Mode

Description added

815 to

819

24.2 DC Characteristics

Table 24.4 DC Characteristics

Description amended

837

24.3.9 HCAN Timing

Table 24.14 HCAN Timing

Description amended

840

24.3.11 AUD Timing

Table 24.16 AUD Timing

Load conditions added

863,

867

Appendix A.1 Address

Table A.1 Address

H’FFFFF526

881,

884 to

886

A.2 Register States in Reset and

Power-Down States

Table A.2 Register States in Reset and Power-Down

States

Description amended

891

Appendix D Package

Dimensions

Figure D.1 Package Dimensions (FP-208A)

Amended

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