MPC8640DEC datasheet(58/140 Pages) FREESCALE

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MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1

Freescale Semiconductor

Figure 32 provides the AC test load for the I2C.

Figure 36. I2C AC Test Load

Figure 37 shows the AC timing diagram for the I2C bus.

Fall time of both SDA and SCL signals

tI2CF

20 + 0.1 Cb

300

Data output delay time

tI2OVKL

—0.9 3

μs

Set-up time for STOP condition

tI2PVKH

0.6

—

μs

Bus free time between a STOP and START condition

tI2KHDX

1.3

—

μs

Noise margin at the LOW level for each connected device

(including hysteresis)

VNL

0.1

× OVDD

—V

Noise margin at the HIGH level for each connected device

(including hysteresis)

VNH

0.2

× OVDD

—V

Note:

1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state)

(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example,

tI2DVKH symbolizes I

2C timing (I2) with respect to the time data input signals (D) reach the valid state (V) relative to

the tI2C clock reference (K) going to the high (H) state or setup time. Also, tI2SXKL symbolizes I

2C timing (I2) for the

time that the data with respect to the start condition (S) went invalid (X) relative to the tI2C clock reference (K) going

to the low (L) state or hold time. Also, tI2PVKH symbolizes I

2C timing (I2) for the time that the data with respect to the

stop condition (P) reaching the valid state (V) relative to the tI2C clock reference (K) going to the high (H) state or

setup time. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).

2. As a transmitter, the MPC8640 provides a delay time of at least 300 ns for the SDA signal (referred to the Vihmin

of the SCL signal) to bridge the undefined region of the falling edge of SCL to avoid unintended generation of Start

or Stop condition. When MPC8640 acts as the I2C bus master while transmitting, MPC8640 drives both SCL and

SDA. As long as the load on SCL and SDA are balanced, MPC8640 would not cause unintended generation of Start

or Stop condition. Therefore, the 300 ns SDA output delay time is not a concern. If, under some rare condition, the

300 ns SDA output delay time is required for MPC8640 as transmitter, the following setting is recommended for the

FDR bit field of the I2CFDR register to ensure both the desired I2C SCL clock frequency and SDA output delay time

are achieved, assuming that the desired I2C SCL clock frequency is 400 KHz and the Digital Filter Sampling Rate

I2C Source Clock Frequency

333 MHz

266 MHz

200 MHz

133 MHz

FDR Bit Setting

0x2A

0x05

0x26

0x00

Actual FDR Divider Selected

896

704

512

384

Actual I2C SCL Frequency Generated

371 KHz

378 KHz

390 KHz

346 KHz

For the detail of I2C frequency calculation, refer to the application note AN2919 “Determining the I2C Frequency

Divider Ratio for SCL”. Note that the I2C Source Clock Frequency is half of the MPX clock frequency for MPC8640.

3. The maximum tI2DXKL has only to be met if the device does not stretch the LOW period (tI2CL) of the SCL signal.

4. Guaranteed by design.

5. CB = capacitance of one bus line in pF.

Table 45. I2C AC Electrical Specifications (continued)

All values refer to VIH (min) and VIL (max) levels (see Table 44).

Parameter

Symbol 1

Min

Max

Unit

Output

Z0 = 50 Ω

OVDD/2

RL = 50 Ω

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