MPC8640DEC datasheet(126/140 Pages) FREESCALE

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MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1

126

Freescale Semiconductor

System Design Information

TSEC2_TXD[4] and TSEC2_TX_ER pins function as cfg_dram_type[0 or 1] at reset and MUST BE

VALID BEFORE HRESET ASSERTION when coming out of device sleep mode.

20.6.1

Special instructions for Single Core device

The mechanical drawing for the single core device does not have all the solder balls that exist on the single

core device. This includes all the balls for VDD_Core1 and SENSEVDD_Core1 which exist on the

package for the dual core device, but not on the single core package. A solder ball is present for

SENSEVSS_Core1 and needs to be connected to ground with a weak (2-10 kΩ) pull down resistor.

Likewise, AVDD_Core1 needs to be pulled to ground as shown in Figure 64.

The mechanical drawing for the single core device is located in Section 16.2, “Mechanical Dimensions of

the MPC8640 FC-CBGA.”

For other pin pull-up or pull-down recommendations of signals, please see Section 17, “Signal Listings.”

20.7

Output Buffer DC Impedance

The MPC8640 drivers are characterized over process, voltage, and temperature. For all buses, the driver

is a push-pull single-ended driver type (open drain for I2C).

To measure Z0 for the single-ended drivers, an external resistor is connected from the chip pad to OVDD

or GND. Then, the value of each resistor is varied until the pad voltage is OVDD/2 (see Figure 66). The

output impedance is the average of two components, the resistances of the pull-up and pull-down devices.

When data is held high, SW1 is closed (SW2 is open) and RP is trimmed until the voltage at the pad equals

OVDD/2. RP then becomes the resistance of the pull-up devices. RP and RN are designed to be close to each

other in value. Then, Z0 = (RP + RN)/2.

Figure 66. Driver Impedance Measurement

OVDD

OGND

Pad

Data

SW1

SW2

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