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PCM3168APAPR Arkusz danych(PDF) 27 Page - Texas Instruments |
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PCM3168APAPR Arkusz danych(HTML) 27 Page - Texas Instruments |
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27 / 66 page ![]() BCKAD/DA (Output) t LRD t DOD 0.5 VDD ´ 0.5 VDD ´ 0.5 VDD ´ 1.4V LRCKAD/DA (Output) DOUT1/2/3 DIN1/2/3/4 t BCH t BCL t BCY t DIS t DIH t DOD t LRS 1.4V 1.4V 0.5 VDD ´ 1.4V BCKAD/DA (Input) LRCKAD/DA (Input) DOUT1/2/3 DIN1/2/3/4 t BCH t BCL t BCY t LRH t DIS t DIH t LRW PCM3168A PCM3168A-Q1 www.ti.com ......................................................................................................................................................................................... SBAS452 – SEPTEMBER 2008 Figure 43. Audio Interface Timing Requirements for Left-Justified, Right-Justified, and I2S Data Formats (Master Mode) Timing Requirements for Figure 43(1) SYMBOL DESCRIPTION MIN TYP MAX UNIT tBCY BCKAD/DA cycle time 1/(64 fS) tBCH BCKAD/DA pulse width high 0.4 tBCY 0.5 tBCY 0.6 tBCY tBCL BCKAD/DA pulse width low 0.4 tBCY 0.5 tBCY 0.6 tBCY tLRD LRCKAD/DA delay time from BCKAD/DA falling edge –10 20 ns tDIS DIN1/2/3/4 setup time to BCKDA rising edge 10 ns tDIH DIN1/2/3/4 hold time to BCKDA rising edge 10 ns tDOD DOUT1/2/3 delay time from BCKAD falling edge –10 20 ns (1) Load capacitance of output is 20 pF. Figure 44. Audio Interface Timing Requirements for DSP and TDM Data Formats (Slave Mode) Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 27 Product Folder Link(s): PCM3168A PCM3168A-Q1 |
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