CS8422 datasheet(31/82 Pages) CIRRUS

31 / 82 page

DS692PP1

CS8422

Figure 18. Differential Receiver Input Structure

6.3

Recovered Master Clock - RMCK

The CS8422 has an internal PLL which recovers a high-frequency system clock, referred to as the recov-

ered master clock (RMCK). RMCK can be generated by incoming AES3-compatible data or the ISCLK

(slave mode and Software Mode only). This clock is used as the master clock source for the AES3 receiver

and the master-mode serial port that it directly supplies data to, and is available as an output on the RMCK

pin. In addition, the user can set the RMCK as the master clock of either of the two remaining serial ports.

6.3.1

Hardware Mode Control

In Hardware Mode, the RMCK frequency is determined by the incoming AES3 frame rate and the

MS_SEL pin. RMCK can be routed for use as the master clock for the serial audio output associated with

SDOUT1 by connecting a 20 k

Ω resistor from the RMCK pin to VL. See “Hardware Mode Control” on

page 39 for more details.

6.3.2

Software Mode Control

In Software Mode, The RMCK frequency is determined by the incoming AES3 frame rate or ISCLK/64

(slave mode only). The RMCK frequency is configured in the register described in Section 11.9 “Recov-

ered Master Clock Ratio Control & Misc. (09h)” on page 52. If the ISCLK is chosen as the source for RM-

CK, then the ratios in the “Recovered Master Clock Ratio Control & Misc. (09h)” register reflect the ratio

of 64*RMCK/ISCLK.

6.4

XTI System Clock Mode

A special clock switching mode is available that allows the clock present at the XTI-XTO clock input to au-

tomatically replace RMCK when the PLL becomes unlocked. This is accomplished without spurious transi-

tions or glitches on RMCK.

When clock switching is enabled, the PLL’s loss of lock will cause the XTI-XTO clock input to be output on

RMCK. If a serial port is set master mode and has RMCK as its master clock source, it’s LRCK and SCLK

(2 2000/N )

Ω

AG N D

RX P[1 :0 ]

(1500 + 1500 /N )

Ω

(2 2000/N )

Ω

RX N [1 :0 ]

(1500 + 1500 /N )

Ω

(22000 /N )

Ω

(22000/N )

Ω

Note:

If RXP/N[1:0] is selected by either the receiver MUX or the TX pass-through MUX, N=1.

If RXP/N[1:0] is selected by both the receiver MUX and the TX pass-through MUX, N=2.

If RXP/N[1:0] is not selected at all, N=0 (i.e. high impedance).

CS8422 Arkusz danych(PDF) 31 Page - Cirrus Logic

CS8422 Arkusz danych(HTML) 31 Page - Cirrus Logic

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82

Arkusz danych Pobierz

Link URL