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VN710SP Arkusz danych(PDF) 6 Page - STMicroelectronics |
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VN710SP Arkusz danych(HTML) 6 Page - STMicroelectronics |
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6 / 11 page ![]() 6/11 VN710SP ISO T/R 7637/1 Test Pulse TEST LEVELS I II III IV Delays and Impedance 1 -25V -50V -75V -100V 2ms, 10 Ω 2 +25V +50V +75V +100V 0.2ms, 10 Ω 3a -25V -50V -100V -150V 0.1ms, 50 Ω 3b +25V +50V +75V +100V 0.1ms, 50 Ω 4 -4V -5V -6V -7V 100ms, 0.01 Ω 5 +26.5V +46.5V +66.5V +86.5V 400ms, 2 Ω ISO T/R 7637/1 Test Pulse TEST LEVELS RESULT III III IV 1 C C C C 2 CCCC 3a CCCC 3b CCCC 4 CCCC 5 C EEE CLASS CONTENTS C All functions of the device are performed as designed after exposure to disturbance. E One or more functions of the device is not performed as designed after exposure and cannot be returned to proper operation without replacing the device. ELECTRICAL TRANSIENTS REQUIREMENTS ON VCC PIN SUGGESTED SCHEME FOR ISO TEST PULSE OUTPUT VCC GND STATUS INPUT ENABLE open from test generator 10K Ω 10K Ω 10K Ω Warning: Input, Enable, Status Pulled to VCC voltage during negative transient. |
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