U4091BM-R datasheet(23/38 Pages) ATMEL

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4872A–CORD–08/05

U4091BM-R

13. Analog-to-Digital Converter (ADC)

This circuit is a 7-bit successive-approximation analog-to-digital converter in switched capacitor

technique. An internal band gap circuit generates a 1.25-V reference voltage which is the equiv-

alent of 1 MSB (1 LSB = 19.5 mV). The possible input voltage at ADIN is 0V to 2.48V.

The ADC needs an SOC (Start Of Conversion) signal. In the High phase of the SOC signal, the

ADC is reset. Then, 50 µs after the beginning of the Low phase of the SOC signal, the ADC gen-

erates an EOC (End Of Conversion) signal which indicates that the conversion is finished. The

rising edge of EOC generates an interrupt at the INT output. The result can be read out by the

serial bus.

Voltages higher than 2.45V have to be divided. The signal connected to the ADC is determined

by 4 bits: ADC0, ADC1, ADC2 and ADC3. TLDR/TLDT measuring is possible relative to a pre-

ceding reference measurement. The current range of IL can be doubled by ADCR. If ADCR is

High, S has the value 0.5, otherwise S = 1.

The source impedance at ADIN must be lower than 250 k

Ω.

Accuracy: 1 LSB + 3%

Figure 13-1. Timing of ADC

Figure 13-2. ADC Input Selection

SOC

µs

EOC

ADIN

0.4 x VB

0.4 x VMP S

0.4 x S AO1

0.4 x VMP

8 x (TLDR - REF)

8 x (TLDT - REF)

0.4 x OFF1

0.4 x OFF2

0.4 x OFF3

IL x 20 mV/(1 mA x S )

ADC

MS B

BIT5

BIT4

BIT3

BIT2

BIT1

LS B

SOC

EOC

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