Address Vector

Applicable to the following core configurations:

Master-Only

Master-Slave

Slave-Only

Yes

Yes

Undefined

The bits in this vector are defined as follows:

6

5

4

3

2

1

0

ADDR_IN[6]

ADDR_IN[5]

ADDR_IN[4]

ADDR_IN[3]

ADDR_IN[2]

ADDR_IN[1]

ADDR_IN[0]

Figure 4: Address Vector

The address vector (ADDR_IN[6:0]) is written with the 7-bit I2C address that will be transmitted during the address phase of the I2C bus transaction.

Data Input Vector

Applicable to the following core configurations:

Master-Only

Master-Slave

Slave-Only

Yes

Yes

Yes

The bits in this vector are defined as follows:

7

6

5

4

3

2

1

0

DATA_IN[7]

DATA_IN[6]

DATA_IN[5]

DATA_IN[4]

DATA_IN[3]

DATA_IN[2]

DATA_IN[1]

DATA_IN[0]

Figure 3: Data Input Vector

The data input vector (DATA_IN[7:0]) is written with a byte that will be transmitted during the data phase of the I2C bus transaction.

Status Vector

Applicable to the following core configurations:

Master-Only

Master-Slave

Slave-Only

Yes

Yes

Yes

The bits in this vector are defined as follows:

Master Only

5

4

3

2

1

0

Not

Implemented

Not

Implemented

Not

Implemented

Not

Implemented

BUSLOSS

SLAVE

TIMEOUT

Master Slave

5

4

3

2

1

0

HDWE_GC

GC_RST

GC_ADDR

GC_BUSY

BUSLOSS

SLAVE

TIMEOUT