LTC1642AIGN datasheet(10/16 Pages) LINER

10 / 16 page

LTC1642A

1642af

APPLICATIO S I FOR ATIO

an internal servo loop adjusts the GATE pin voltage such

that Q1 acts as a constant current source. The voltage limit

across R2 increases as the output charges; this foldback

in the current limit helps to even out Q1’s power dissipa-

tion. The output is sensed at the FB pin. When FB is

grounded, the sense voltage is limited to 26mV. When FB

is greater than 0.7V, the limit is 56mV and the full depen-

dence is shown in Figure 3.

When the sense resistor voltage is 3mV below its limit, the

circuit breaker timer starts. Once BRK TMR reaches its

threshold, the circuit breaker opens, the GATE pin is pulled

to ground (cutting off Q1) and FAULT is asserted.

The parameter VCB specified in the DC electrical character-

istics refers to the voltage difference between the VCC and

SENSE pins needed to start the circuit breaker timer. The

limiting value maintained by the servo loop is 3mV higher

than VCB.

Should the sense resistor voltage drop below its limit

before the timer trips, the GATE voltage begins ramping

back up immediately and the BRK TMR pin returns to

ground. However, due to the slow gate ramp, Q1 continues

to dissipate substantial power for some time. Connecting

R10 in series with timing capacitor C4 (as shown in

Figure 1) ensures that the circuit breaker trips in the event

of repetitive, but brief, load shorts. The delay before the

circuit breaker opens is:

tBRKTMR = C4 (61kΩ – R10).

Once the circuit breaker trips, GATE and FAULT remain at

ground until the chip is restarted. To restart, hold the ON

pin low for at least 2

µs and FAULT will go high. Then take

ON high again and the GATE will ramp up after a system

timing cycle. Or, configure the LTC1642A to restart itself

after the circuit breaker trips by connecting FAULT to the

ON pin, as shown in the next section.

The servo loop controlling Q1 during current limit has a

unity-gain frequency of about 125kHz. In Figure 1, R4 and

C2 provide compensation. To ensure stability the product

1/(2 •

π • R4 • C2) should be kept below the unity-gain

frequency, and C2 should be more than Q1’s input capaci-

tance CISS. A good starting point for C2 is 0.047µF and R4

is 330

Ω. Keep R4 ≥ 100Ω.

Typical waveforms during a load short to ground are

shown in Figure 4. The load is shorted to ground at time 1.

The GATE voltage drops until the load current equals its

maximum limit, and the circuit breaker timer starts. The

short is cleared at time 2, before the timer trips. The BRK

TMR pin returns to ground, and the GATE voltage begins

ramping up. At time 3 the load is shorted again and at time

4 the timer trips, pulling the GATE to ground and asserting

FAULT. Although the short is cleared at time 5, FAULT

doesn’t go high until the ON pin is pulled low at time 6. At

time 7 ON goes high and the system timer starts. When it

trips at time 8 the GATE voltage begins ramping.

To disable current limit and electronic circuit breaker

protection, tie the SENSE pin to VCC, the BRK TMR pin to

GND and omit compensating resistor R4.

FB PIN VOLTAGE (mV)

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

1642a F03

Figure 3. Foldback Current Limit

Figure 4. Current Limit and Circuit Breaker Timing

40ms/DIV

1642a F04

t5 t7

RST TMR

2V/DIV

20V/DIV

FAULT

20V/DIV

BRK TMR

2V/DIV

VOUT

20V/DIV

GATE

20V/DIV

ILOAD

5A/DIV

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