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Zakładka z wyszukiwarką danych komponentów |
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Zakładka z wyszukiwarką danych komponentów |
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TL16C554FN Arkusz danych(PDF) 13 Page - Texas Instruments |
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TL16C554FN Arkusz danych(HTML) 13 Page - Texas Instruments |
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13 / 33 page  TL16C554, TL16C554I ASYNCHRONOUS COMMUNICATIONS ELEMENT SLLS165D – JANUARY 1994 – REVISED JULY 1998 13 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PARAMETER MEASUREMENT INFORMATION Stop td9 (see Note A) tpd4 Top Byte of FIFO tpd4 td9 Active Active Sample Clock INTx (time-out or trigger level) Interrupt IOR (RD RBR) IOR (RD LSR) Previous BYTE Read From FIFO Active (FIFO at or above trigger level) (FIFO below trigger level) RXx INTx Interrupt 50% 50% 50% 50% 50% 50% 50% NOTE A: This is the reading of the last byte in the FIFO. Figure 11. Receiver FIFO After First Byte (After RDR Set) Waveforms Active (see Note A) Stop td9 (see Note B) tpd5 IOR (RD RBR) Sample Clock RXRDY RXx 50% 50% 50% NOTES: A. This is the reading of the last byte in the FIFO. B. If FCR0 = 1, then td9 = 3 RCLK cycles. For a time-out interrupt, td9 = 8 RCLK cycles. Figure 12. Receiver Ready Mode 0 Timing Waveforms |
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