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TLV5633CDWG4 Arkusz danych(PDF) 6 Page - Texas Instruments |
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TLV5633CDWG4 Arkusz danych(HTML) 6 Page - Texas Instruments |
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6 / 23 page ![]() www.ti.com DIGITAL INPUT TIMING REQUIREMENTS PARAMETER MEASUREMENT INFORMATION X Data X X Address X tsu(D) tsu(A) th(DA) twH(WE) tsu(WE-LD) tw(LD) tsu(CS-WE) D(0-7) A(0,1) CS WE LDAC LSW X X MSW X 0 X X 1 X D(0-7) A(0,1) CS WE LDAC TLV5633C TLV5633I SLAS190C – MARCH 1999 – REVISED SEPTEMBER 2006 MIN NOM MAX UNIT tsu(CS-WE) Setup time, CS low before negative WE edge 15 ns tsu(D) Setup time, data ready before positive WE edge 10 ns tsu(A) Setup time, addresses ready before positive WE edge 20 ns th(DA) Hold time, data and addresses held valid after positive WE edge 5 ns tsu(WE-LD) Setup time, positive WE edge before LDAC low 5 ns twH(WE) Pulse duration, WE high 20 ns tw(LD) Pulse duration, LDAC low 23 ns Figure 1. Timing Diagram Figure 2. Example of a Complete Write Cycle (MSW, LSW) Using LDAC for Update 6 Submit Documentation Feedback |
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