TMS320VC549 datasheet(13/60 Pages) TI

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TMS320VC549

FIXEDPOINT DIGITAL SIGNAL PROCESSOR

SPRS078F – SEPTEMBER 1998 – REVISED MAY 2000

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

PARAMETER MEASUREMENT INFORMATION

timing parameter symbology

Timing parameter symbols used are created in accordance with JEDEC Standard 100-A. To shorten the

symbols, some of the pin names and other related terminology have been abbreviated as follows:

Lowercase subscripts and their meanings:

Letters and symbols and their meanings:

access time

High

cycle time (period)

Low

delay time

Valid

dis

disable time

High impedance

enable time

fall time

hold time

rise time

setup time

transition time

valid time

pulse duration (width)

Unknown, changing, or don’t care level

signal transition reference points

All timing references are made at a voltage of 1.5 volts, except rise and fall times which are referenced at the

10% and 90% points of the specified low and high logic levels, respectively.

Tester Pin

Electronics

VLoad

IOL

IOH

Output

Under

Test

Ω

Where: IOL

= 1.5 mA (all outputs)

IOH

= 300

µA (all outputs)

VLoad = 1.5 V

= 40 pF typical load circuit capacitance.

Figure 1. 3.3-V Test Load Circuit

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