November 2006

P2040C

rev 1.6

LCD Panel EMI Reduction IC

2 of 9

Notice: The information in this document is subject to change without notice.

MRA

SSON#

ModOUT

SR0

1

2

3

4

5

6

7

8

P2040C

CLKIN

VSS

1

2

3

4

5

6

7

8

P2040C

SR1

VDD

Pin Configuration

Pin Description

Pin#

Pin

Name

Type

Description

1

CLKIN

I

External reference frequency input. Connect to externally generated reference signal.

2

MRA

I

Digital logic input used to select modulation rate. This pin has an internal pull-up resistor.

3

SR1

I

Digital logic input used to select Spreading Range. This pin has an internal pull-up resistor.

4

VSS

P

Ground to entire chip. Connect to system ground.

5

SSON#

I

Digital logic input used to enable Spread Spectrum function (Active LOW). Spread Spectrum

function enabled when LOW, disabled when HIGH. This pin has an internal pull-low resistor.

6

ModOUT

O

Spread spectrum Clock Output.

7

SR0

I

Digital logic input used to select Spreading Range. This pin has an internal pull-up resistor.

8

VDD

P

Power supply for the entire chip.

Modulation Selection (Commercial) – Table 1

Spreading Range

MRA

SR1

SR0

54MHz

65MHz

81MHz

140MHz

162MHz

Modulation Rate

0

0

0

±1.4%

±1.2%

±1.0%

±0.6%

±0.4%

(Fin/80) * 62.49KHz

0

0

1

±2.0%

±1.9%

±1.6%

±1.0%

±0.8%

(Fin/80) * 62.49KHz

0

1

0

±1.1%

±0.9%

±0.5%

±0.3%

±0.3%

(Fin/80) * 62.49KHz

0

1

1

±1.8%

±1.5%

±1.0%

±0.54%

±0.4%

(Fin/80) * 62.49KHz

1

0

0

±1.3%

±1.3%

±1.3%

±1.25%

±1.1%

(Fin/80) * 20.83KHz

1

0

1

±2.2%

±2.1%

±2.1%

±2.0%

±1.8%

(Fin/80) * 20.83KHz

1

1

0

±1.4%

±1.3%

±1.4%

±1.2%

±0.9%

(Fin/80) * 20.83KHz

1

1

1

±2.1%

±2.1%

±2.1%

±1.9%

±1.4%

(Fin/80) * 20.83KHz