TMP112 datasheet(13/24 Pages) TI

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NOISE

TMP112

SCL

SDA

GND

V+

ALERT

ADD0

10nF

SupplyVoltage

TIMING DIAGRAMS

TMP112

www.ti.com ......................................................................................................................................................... SBOS473B – MARCH 2009 – REVISED JUNE 2009

Start Data Transfer: A change in the state of the

SDA line, from high to low, while the SCL line is high,

The TMP112 is a very low-power device and

defines a START condition. Each data transfer is

generates very low noise on the supply bus. Applying

initiated with a START condition.

an RC filter to the V+ pin of the TMP112 can further

reduce any noise that the TMP112 might propagate

Stop Data Transfer: A change in the state of the

to other components. RF in Figure 14 should be less

SDA line from low to high while the SCL line is high

than 5k

Ω and CF should be greater than 10nF.

defines a STOP condition. Each data transfer is

terminated

with

repeated

START

STOP

condition.

Data Transfer: The number of data bytes transferred

between a START and a STOP condition is not

limited and is determined by the master device. It is

also possible to use the TMP112 for single byte

updates. To update only the MS byte, terminate the

communication

issuing

START

STOP

communication on the bus.

Acknowledge:

Each

receiving

device,

when

addressed, is obliged to generate an Acknowledge

bit. A device that acknowledges must pull down the

SDA line during the Acknowledge clock pulse in such

a way that the SDA line is stable low during the high

Figure 14. Noise Reduction Techniques

period of the Acknowledge clock pulse. Setup and

hold times must be taken into account. On a master

receive, the termination of the data transfer can be

signaled

the

master

generating

Not-Acknowledge ('1') on the last byte that has been

The TMP112 is two-wire and SMBus compatible.

transmitted by the slave.

Figure

describe

the

various

operations on the TMP112. Parameters for Figure 15

are defined in Table 13. Bus definitions are:

Bus Idle: Both SDA and SCL lines remain high.

Table 13. Timing Diagram Definitions

FAST MODE

HIGH-SPEED MODE

PARAMETER

TEST CONDITIONS

MIN

MAX

MIN

MAX

UNIT

f(SCL)

SCL Operating Frequency, VS > 1.7V

0.001

0.4

0.001

3.4

MHz

f(SCL)

SCL Operating Frequency, VS < 1.7V

0.001

0.4

0.001

2.75

MHz

Bus Free Time Between STOP and START

t(BUF)

600

160

Condition

Hold time after repeated START condition.

t(HDSTA)

100

After this period, the first clock is generated.

t(SUSTA)

Repeated START Condition Setup Time

100

t(SUSTO)

STOP Condition Setup Time

100

t(HDDAT)

Data Hold Time

t(SUDAT)

Data Setup Time

100

t(LOW)

SCL Clock Low Period, VS > 1.7V

1300

160

t(LOW)

SCL Clock Low Period, VS < 1.7V

1300

200

t(HIGH)

SCL Clock High Period

600

Clock/Data Fall Time

300

Clock/Data Rise Time

300

160

Clock/Data Rise Time for SCLK

≤ 100kHz

1000

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