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SPT7935

Figure 1 – Timing Diagram

N+8

N+7

N+6

N+2

N+1

N

N-1

N-2

N-1

N

Sampling Points

CLK

GENERAL DESCRIPTION

The SPT7935 is an ultra-low power, 12-bit, 20 MSPS ADC.

It has a pipelined architecture and incorporates digital error

correction of the 11 most significant bits. This error correction

ensures good linearity performance for input frequencies up

to Nyquist. The inputs are fully differential, making the device

insensitive to system-level noise. This device can also be

used in a single-ended mode. (See analog input section.)

With the power dissipation roughly proportional to the sam-

pling rate, this device is ideal for very low power applications

in the range of 1 to 20 MSPS.

TYPICAL INTERFACE CIRCUIT

The SPT7935 requires few external components to achieve

the stated operation and performance. Figure 2 shows the

typical interface requirements when using the SPT7935 in

normal circuit operation. The following sections provide

a description of the functions and outline critical perform-

ance criteria to consider for achieving the optimal device

performance.

ANALOG INPUT

The input of the SPT7935 can be configured in various ways

depending on if a single-ended or differential, AC- or DC-

coupled input is desired.

Figure 2 – Typical Interface Circuit

GND

.01

µF

+

4.7

µF

Ref– In

(+1.15 V)

Ref+ In

(+2.15 V)

.01

µF

+

10

µF

0.1

µF

+3.3 V

CLK In

(3 V Logic)

Interfacing

3 V Logic

Decoupling Cap

+3.3 V

DGND

FB

(MSB)

AGND

U1

SPT7935

.01

µF

(+1.65 V)

Minicircuit

T1-6T

RF In

51

68 pF

22

23

11

12

34

33

1

44

(LSB)

N/C

N/C

N/C

GND

Bias1

Bias2

GND

GND

D0

D1

D2

D3

D4

D5

D6

D7

D8

D9

.01

µF

+

4.7

µF

+3.3 V Digital

9.5

µA

90

µA

FB = Ferrite Bead; must be placed as close to U1 as possible.