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Zakładka z wyszukiwarką danych komponentów |
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Zakładka z wyszukiwarką danych komponentów |
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SP3508 Arkusz danych(PDF) 27 Page - Exar Corporation |
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SP3508 Arkusz danych(HTML) 27 Page - Exar Corporation |
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27 / 36 page  27 Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (50)668-707 • www.exar.com SP3508_00_072208 The same receivers also incorporate a ter- mination network internally for V.35 applica- tions.ForV.35,thereceiverinputtermination is a “Y” termination consisting of two 51Ω resistors connected in series and a 124Ω resistor connected between the two 50Ω resistors and GND. The receiver itself is identical to the V. receiver. The differential receivers can be configured to be ITU-T-V.0 single-ended receivers by internally connecting the non-inverting input to ground. This is internally done by default from the decoder. The non-inverting input is rerouted to V0GND and can be grounded separately. The ITU-T-V.0 receivers can operate over 20Kbps and are used in RS- 449/V.36, EA-530, EA-530A and X.2 modes as Category II signals as indicated by their corresponding specifications. All receivers include an enable/disable line for disabling the receiver output allowing convenient half-duplex configurations. The enable pins will either enable or disable the output of the receivers according to the ap- propriate active logic illustrated on Figure 44. The receiver’s enable lines include an internalpull-uporpull-downdevice,depend- ing on the active polarity of the receiver, that enables the receiver upon power up if the enable lines are left floating. During disabled conditions, the receiver outputs will be at a high impedance state. If the receiver is disabled any associated termination is also disconnected from the inputs. All receivers include a fail-safe feature that outputs a logic high when the receiver inputs FEATURES are open, terminated but open, or shorted together. For single-ended V.28 and V.0 receivers, there are internal 5kΩ pull-down resistors on the inputs which produces a logic high (“”) at the receiver outputs. The differential receivers have a proprietary cir- cuit that detect open or shorted inputs and if so, will produce a logic HIGH (“”) at the receiver output. CHARGE PUMP SP3508 uses an internal capacitive charge pump to generate Vdd and Vss. The design is a patented (5,306,954) four-phased volt- age shifting charge pump converters that converts the input voltage of 3.3V to nomi- nal output voltages of +/-6V (Vdd & Vss). SP3508 also includes an inverter block that inverts Vcc to -Vcc (Vss2). There is a free-running oscillator that controls the four phases of the voltage shifting. A description of each phase follows. 4-phased doubler pump Phase 1 -V SS charge storage -During this phase of theclockcycle,thepositivesideofcapacitors C and C2 are initially charged to V CC. C+ is then switched to ground and the charge in C- is transferred to C2-. Since C2+ is con- nected to V CC, the voltage potential across capacitor C2 is now 2xV CC. V CC = +3V –3V –3V +3V V SS1 Stora ge C apacitor V DD Stora ge C apacitor C 1 C 2 + + + + – – – – C VDD C VSS1 Figure 45. Charge Pump - Phase . |
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